1. Field of the Invention
The present invention generally relates to arithmetic units for digital computers and, more particularly, to the implementation of a compact, high speed, fully static 64-bit integer adder for advanced microprocessors.
2. Description of the Prior Art
In the design and implementation of advanced microprocessors, one of the primary building blocks is an integer adder. It is used as a building block in a fixed point unit, a load/store address generation unit, and in the design of a floating point adder and multiplication unit. Various width integer adds are required from 16-bit to 64-bit to even 128-bit lengths. Furthermore, ah integer comparator is easily formed as a degenerate case of the integer adder and is a second high use building block. It is therefore desirable to generalize the construction and design of the adder unit so that all the functional units can benefit from the design time and physical layout effort involved to design and develop a state-of-the art adder design.